The present invention relates to an operation of a non-volatile memory device and, more particularly, to a method of operating a non-volatile memory device, in which data of a sensing node is inverted and stored.
A well-known NAND flash memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array consists of a plurality of word lines extending along rows, a plurality of bit lines extending along columns, and a plurality of cell strings corresponding to the bit lines.
A string select line, the word lines, and the row decoder coupled to a common source line are positioned on one side of the memory cell array. The page buffer coupled to the plurality of bit lines is positioned on the other side of the memory cell array.
In recent years, in order to further increase the integration degree of the flash memory device, active research has been conducted on a multi-bit cell that is able to store a plurality of data bits in one memory cell. This type of a memory cell is called a multi-level cell (hereinafter referred to as ‘MLC’). A memory cell that stores a single bit of data is called a single level cell (hereinafter referred to as ‘SLC’).
FIG. 1A shows cell distributions of a SLC memory device.
Referring to FIG. 1A, the SLC has two kinds of erase and program cell states 101, 102 (cell distributions). The erase state 101 of the cells shift to the program cell state 102 according to a program operation (S110). The SLC requires one program operation, as shown in FIG. 1A, and the program operation can be verified by performing one verification operation with respect to a verify voltage PV1.
FIG. 1B shows cell distributions of a MLC memory device.
Referring to FIG. 1B, cell distributions of MLCs are able to store 2-bit data. The cells have cell states 111 to 114 with data storage states [11], [10], [00], and [01]. The distributions correspond to threshold voltage distributions of the MLCs.
Each cell is programmed to have a state from the state [11] (111) to the state [10] (112) by performing a least significant bit (LSB) program operation (S121). A most significant bit (MSB) program operation is performed for the cell to change a state from the state [10] (112) to the state [00] (113) (S131) or to change a state from the state [11] (111) to the state [01] (114) (S132).
After the program operation, verification is performed on the cell. In general, as the number of data bits that can be stored increases, cell distributions increase and, therefore, the number of verifications also increases.
As mentioned earlier, in the case of a SLC, verification is performed on a program 1 pulse. However, in the case of a MLC that is able to store 2-bit data as shown in FIG. 1B, two verification operations are required for a program 1 pulse in a MSB program operation. Similarly, a 3-bit MLC requires three verification operations and a 4-bit MLC requires eight verification operations, with respect to a program pulse.
The number of program verification operations increases as the number of bits that can be stored in a memory cell increases. Thus, the time required for program verification is also increased.